A2179 2020 MacBook Air

820-01958 Power Sequence
Once a valid external power source (Charger or battery) is connected, the following rails will come online.

PPBUS_G3H: Normal voltage is ~12.6v on the charger with the battery disconnected. Produced from the ISL9240 (U7000, which uses PPDCIN_G3H as its VIN.

PP3v3_G3H_RTC: Normal voltage is ~3.3v. Produced from U6960, which uses PPBUS_G3H as its VIN.

PP3v3_G3H: Normal voltage is ~3.3v. Produced from U7650/Q7680.

Once the PMU (U7800) receives power from PP3v3_G3H, it will initialize and begin producing rails to power the T2 chip.

''Important note! DDR/CPU rails here are referring to the T2 chip, which is basically a CPU with its own RAM in a package on package design. These rails are not referring to the Intel CPU or system RAM.''

PP1v8_SLP_S2R: Normal voltage is ~1.8v. Produced from U7800.

PP1v8_AWAKE: Normal voltage is ~1.8v. Produced from U7800.

PP1v8_SLPS2R_PMUGPIO: Normal voltage is ~1.8v. Produced from U7800.

PP1v1_SLPS2R: Normal voltage is ~1.1v. Produced from U7800.

PP0v8_SLPS2R: Normal voltage is ~0.8v. Produced from U7800.

PP0v82_SLPDDR: Normal voltage is ~0.82v. Produced from U7800.

PP3v3_AWAKE: Normal voltage is ~3.3v. Produced from U7800.

PPVDDCPUSRAM_AWAKE: Normal voltage is ~1.06v. Produced from U7800.

PP0v9_SLPDDR: Normal voltage is ~0.9v. Produced from U7800.

PP1v1_SLPDDR: Normal voltage is ~1.1v. Produced from U7800.

PP1v2_AWAKE: Normal voltage is ~1.2v. Produced from U7800.

PPVDDCPU_AWAKE: Normal voltage is ~1.06v. Produced from U7800.

Once the T2 is powered from the above rails, it will read its ROM (U4770.) The T2 will then begin to start its boot up process, in which we will initialize the below rails.

PP3v_G3H: Normal voltage is ~3.0v. Produced from U7800, powers some PCH functions.

PP5v_G3S: Normal voltage is ~5v. Produced from U7650/Q7660.

PP3v3_G3S: Normal voltage is ~3.3v. Produced from U8210.

PP1v8_G3S: Normal voltage is ~1.8v. Produced from U8220.

The SSD power is then enabled to allow the T2 to boot BridgeOs.

PP1v8_VCCQIO_SSD0: Normal voltage is ~1.8v. Produced from U7800.

PP0v9_SSD: Normal voltage is ~0.9v. Produced from U7800.

PPVCC_NAND_SSD0: Normal voltage is ~2.5-2.7v. Produced from U9060.

'''Once the SSD is powered, and BridgeOs boots, the T2 will signal the device to power on if the power button is pressed. The 820-01958 will assert the pwrbtn signal if the charger is plugged in with the battery disconnected and auto start given the device is in functional condition. We will then expect the following rails once the machine is at this stage in the power up sequence. These rails will primarily power the PCH section of the CPU. NOTE: BridgeOs failing to boot will result in the following rails to be missing.'''

PP3v3_S5: Normal voltage is ~3.3v. Produced from U7800.

PP1v8_PRIM_PCH: Normal voltage is ~1.8v. Produced from U7700.

The PCH will then de-assert (pull low) PM_SLP_S4_L and PM_SLP_S5_L momentarily to enable the next stage in the power sequence.

PP1v8_S3: Normal voltage is ~1.8v. Produced from U8250. (Powers system RAM.)

PP1v1_S3: Normal voltage is ~1.2v. Produced from U8100/Q8100. (Powers system RAM.)

PP0v6_S3: Normal voltage is ~0.6v. Produced from U8150. (Powers system RAM.)

The PCH will then de-assert (pull low) PM_SLP_S3_L and PM_SLP_S0_L momentarily to enable the final stage in the power up sequence.

PPVCCIN_AUX_PCH: Normal voltage is ~1.8v. Created from U7400/Q7401. Incidence in power sequence unknown, likely comes online before the rest of the PCH rails. Likely powers internal level shifting in the PCH.

PP1v05_PCH_CPU : Normal voltage is ~1.05v. Likely internally created within the PCH, sourced from another rail generated from U7800. May explain "clicking" sound when these boards experience CPU failure.

PP1v1_S0SW: Normal voltage is ~1.0v. Produced from U8240.

PP1v8_S0SW_CPU: Normal voltage is ~1.8v. Produced from U8245.

PPVCC_S0_CPU: Normal voltage is ~1.8v, but can drop when the CPU is under load. Produced from U7100/U7210/U7220/U7230.